The invention relates to a logic circuit.
Many applications require determining if a test word having of n bits matches a reference word having of the same number of bits. For this purpose, the i-th bit of the test word may be connected to a first input of an i-th XOR-gate and the i-th bit of the reference word may be connected to a second input of the i-th XOR-gate and the outputs of the XOR-gates may be coupled through AND-gates resulting in a single bit, which indicates whether the test word matches the reference word. A partial match will result in a mismatch. This comparison may be performed within a single cycle.
However, depending on the application it may be desirable to have an indication of the extent the test word matches the reference word. This may be called a match quality indication. For example, if fifty percent of the bits of the test word are identical to the reference word, producing the indication may require changing every combination of bits of the reference word one after the other and comparing the resulting reference words with the test bits. Accordingly, it is very time consuming. Hence, there may be a need for a faster quality indication approach.